Communication receivers that recover digital signals must sample an analog waveform and then reliably detect the sampled data. Signals arriving at a receiver are typically corrupted by intersymbol interference (ISI), crosstalk, echo, and other noise. As data rates increase, the receiver must both equalize the channel, to compensate for such corruptions, and detect the encoded signals at increasingly higher clock rates. Decision-feedback equalization (DFE) is a widely used technique for removing intersymbol interference and other noise at high data rates. For a detailed discussion of decision feedback equalizers, see, for example, Digital Communication Principles by R. Gitlin et al (Plenum Press 1992) and Digital Communications by E. A. Lee and D. G. Messerschmitt (Kluwer Academic Press, 1988), each incorporated by reference herein in their entirety.
Generally, decision-feedback equalization utilizes a nonlinear equalizer to equalize the channel using a feedback loop based on previously detected (or decided) data. In one typical DFE implementation, a received analog signal is sampled after DFE correction and compared to one or more thresholds to generate the detected data. The DFE correction, is subtracted in a feedback fashion to produce a DFE-corrected signal. A clock, generated from the received signal by a Clock and Data Recovery (CDR) circuit, is generally used to sample the DFE-corrected signal and for the DFE operation. An example of such a receiver is disclosed in “Method and Apparatus for Generating One or More Clock Signals for a Decision-Feedback Equalizer Using DFE Detected Data”, by Aziz et al, U.S. Pat. No. 7,616,686, incorporated by reference herein in its entirety. The receiver described in the patent utilizes a DFE-based phase detection architecture for clock and data recovery of a DFE equalized signal.
A DFE-based receiver usually includes an analog front end (AFE), typically having an adjustable gain amplifier (AGA) used to control the input signal level, and an equalizer used to compensate for linear, frequency-based distortions in the input signal to the receiver. The equalizer (also referred to herein as a continuous time linear equalizer or CTLE) is generally implemented as an analog-based filter with at least one adjustable coefficient or peaking parameter that can at least partially compensate for linear distortions in the received signal. For example, high frequency portions of the received signals might be attenuated as the signals pass through a transmission line, rounding off what are otherwise sharp, square-wave signals as originally transmitted. The CTLE's coefficients or peaking parameters, in response to a controller within the receiver, are adjusted to add gain to the high frequency components of the signal, referred to herein as “peaking”, to at least partially restore the received signal to its original shape. However, the analog circuitry in the AFE might have inherent limitations, one of which is the amount of nonlinear distortion introduced onto the received signal by various analog circuits in the AFE. Any distortion introduced by the AFE can seriously degrade performance of the overall receiver. For example, should one or more amplifiers in the AFE begin to saturate, i.e., limit signals into or out of the amplifiers, nonlinear distortion of the input signal results. Conversely, an analog amplifier widely used in CTLE implementations can generate significant nonlinear distortion when the amplifier is operating at low gain.
Thus, it is desirable to provide a variable gain amplifier design, useful in a CTLE applications or the like, that does not cause significant nonlinear distortion at low gain.